This invention concerns a dynamic threshold voltage MOS transistor (insulated gate Transistor) fitted with an integrated current limiter. This device is intended in particular to be made on an SOI (silicon on insulator) type substrate, in other words a substrate having a thin surface layer of silicon insulated by an underlying layer of oxide.
The invention also concerns a process for making such a device in a particularly compact form with a view to integrating it into a circuit.
The invention finds applications particularly in the manufacture of CMOS circuits operating with very low supply voltages such as for example micro-processors or digital signal processors (DSP).
The prior art is shown particularly in documents (1), (2), (3) and (4) mentioned below and the references for which are given at the end of this description.
A usual MOS transistor may be considered as being made up of two intrinsic components. The first component is the MOS transistor itself, in which the current, controlled by the gate, flows between the drain and the source, and in which the substrate is subject to fixed polarisation. The second component is a bipolar parasitic transistor for which the drain and the source act as transmitter and collector, and the substrate acts as the base.
Document (1) proposes the simultaneous activation of the MOS component and the bipolar component so as to increase the total current supplied by the device, and to do this by connecting the transistor gate to its substrate. Such a device is however little used on account of the significant increase in static current related to the operation of the bipolar component. Indeed, minimal static current is generally required in CMOS circuits.
Document (2) proposes a hybrid mode of operation of the MOS and shows that, by means of the connection between the gate and the substrate, the threshold voltage of the MOS may be lowered and the transistor characteristic gradient under the threshold may be improved at low voltage, in other words before the bipolar transistor is activated. This operational principle has given rise to the dynamic threshold voltage transistor described in document (3) xe2x80x9cDynamic Threshold Voltage MOSFETxe2x80x9d or xe2x80x9cDTMOSxe2x80x9d.
The symbolic electrical diagram of a dynamic threshold voltage MOS transistor (DTMOS) is shown in the appended FIG. 1.
The transistor 10 comprises, like any MOS transistor, a drain terminal 12, connected to a source terminal 14 by a channel, and a gate terminal 16 to control the current passing through the channel.
Moreover, an electrical connection 18 is established between the gate and the substrate. In the figure a substrate contact terminal to which the electrical connection 18 is connected is identified with the reference 11.
The threshold voltage Vt of a MOS transistor depends on the voltage applied on its substrate.
As shown in document (4), the voltage Vt may be expressed by the following relation.
Vt=Vfb+2xcfx86f+xcex3{square root over (2xcfx86fxe2x88x92Vbs)}
In this expression, Vfb is the flat band voltage, xcfx86f is the Fermi potential, xcex3 is the substrate effect coefficient and Vbs is the potential difference applied between the substrate and the transistor source.
When the gate is connected to the substrate as is the case for the DTMOS, the voltage applied to the gate is also applied to the substrate. The threshold voltage is then dependent on the voltage applied to the gate, which justifies the term xe2x80x9cdynamic threshold voltage transistorxe2x80x9d.
During normal operation, in respect of an NMOS transistor, taken here by way of illustration, the polarisation applied to the gate is positive relative to the source. It brings about the forward bias of the junction existing between substrate and source, and possibly the forward bias of the junction between substrate and drain (depending on the polarisation applied to the drain). If high voltage is applied to the gate, the same voltage applied to the substrate causes a significant current to pass in the junction. This contributes to the increase in total static current in a circuit fitted with the DTMOS component.
The maximum acceptable current for a DTMOS in SOI technology is about 0.6 V, so as to limit this junction current to approximately 100 pA per micrometer of transistor width. Using a DTMOS at a higher supply voltage requires a device to be inserted which enables the junction current to be reduced. Such a device is inserted between the gate and the substrate and is called a current limiter. Reference may be made on this subject to document (3).
The current limiter is a second MOS transistor for which different configurations of polarisation are conceivable.
A first proposed configuration is shown in the appended FIG. 2.
FIG. 2 shows the MOS transistor 10 of FIG. 1, which is fitted with a current limiter in the form of a second MOS transistor 20 inserted between the gate terminal 16 and the substrate terminal 11.
The gate 26 of the second transistor is polarised at the supply voltage in the case of an NMOS transistor and is polarised at the earth in the case of a PMOS transistor.
Another possible polarisation configuration of the second transistor is shown in the appended FIG. 3.
It is distinguished from the configuration in FIG. 2 essentially in that the gate 26 of the second transistor 20 is henceforth connected to its source.
It should be specified that the second transistor 20 is a conventional transistor providing no access to the substrate. Its substrate is floating.
One essential difficulty related to the manufacture of a device according to the diagrams in FIG. 2 or 3 lies in the fact that making the limiter transistor and the connections with the first transistor is incompatible with the requirements for reducing the sizes of components.
Indeed, the search for an ever greater integration density of components does not allow the electrical diagram of the devices mentioned above to be transcribed directly in an integrated version.
The purpose of the present invention is to propose a DTMOS transistor device with current limiter, which. does not have the difficulties above and is able to be made in the form of an integrated circuit.
A particular purpose is to propose a device of this type which allows the number and range of connections required between the transistors to be reduced, so as to allow it to be made compactly.
Another purpose is propose a particularly cost-effective process for manufacturing the device.
To fulfil these purposes, a more precise object of the invention is a semi-conductor device, comprising on a substrate:
a first dynamic threshold voltage MOS transistor with a gate, and a channel of a first conductivity type, and
a current limiter means connected between the gate and the channel of said first MOS transistor.
In accordance with the invention, the first MOS transistor is fitted with a first doped zone of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone of a second conductivity type, placed against the first doped zone and electrically connected to the first doped zone by an ohmic connection path.
In terms of the invention, the ohmic connection between the first and second doped zones of a simple connection is distinguished by physical contact resulting from the juxtaposition of these areas.
The ohmic connection may be made, for example, by a layer of electrically conductive material, such as a layer of silicide, which connects the first and second doped zones to each other.
In a particular embodiment of the device of the invention, the current limiter means may be a second MOS transistor. In this case, the second doped zone and a third doped zone of the same conductivity type as the second doped zone may form the source and drain of said transistor.
Between the source and drain of the second transistor, in other words between the second and third doped zones, is a channel area of an opposite conductivity type, that is to the first conductivity type. The doping concentration of the channel is however lower than that of the source and drain.
According to different configurations of polarisation, the gate of the second transistor may be connected to a gate polarisation terminal or to the second doped zone, in other words to the source of the second transistor.
In this second case, a common connection terminal may be provided both for the gate and the second doped zone.
The third doped zone, in other words here the drain of the second transistor, may be connected to the gate of the first transistor.
In another particular embodiment of the invention device, the current limiter means may further be a diode. The second doped zone and a third doped zone, of an opposite conductivity type to that of the second doped zone, then form the terminals of the diode.
While the second and third doped zones have a relatively high doping concentration, they may be separated by a fourth doped zone having a lower doping concentration.
While the second and third doped zones are of an opposite conductivity type, the fourth zone may be either of the conductivity type of the second zone, or of that of the third zone.
The effect of the fourth zone is thus to extend one of the second or third doped zones so as to form a junction of the P+N or N+P type.
Just as in the previously described embodiment, the third doped zone may be connected to the gate of the first MOS transistor.
Furthermore, according to a particular embodiment of the diode, the latter may be fitted with a gate extending over the fourth doped zone. This gate does not really have an electrical function but may act, as will emerge in the following description, as an implantation mask of the second and third doped zones, in order to preserve the fourth doped zone.
The diode gate may be left floating or may be connected to one of the diode terminals, in other words to one of the second and third doped zones.
The invention also concerns a process for manufacturing a device such as previously described.
Where the device comprises a current limiter in the form of an MOS transistor, the process comprises the following successive stages:
a) preparation in a substrate of an active zone, intended to receive the first and second transistors and having a first conductivity type,
b) formation of a first and a second gate above the active zone, corresponding to the first and second transistors respectively, the gates being separated from the substrate by a gate insulator and covering channel areas of the first and second transistors respectively,
c) formation of first and second source and drain areas of a second conductivity type opposite to the first conductivity type, corresponding to the first and second transistors respectively, by self-aligned ion implantation on the first and second gates, and formation of the first doped zone of the first conductivity type, in contact with the channel of the first transistor and adjacent to one of the source and drain areas of the second transistor, by self-aligned ion implantation on the gate of the first transistor,
d) formation of a conductive layer in electrical contact with the first doped zone and one of the source and drain areas of the second transistor adjacent to said first doped zone, so as to connect them electrically.
By self-aligned implantation on a gate is understood an implantation during which the gate is used at least partially as an implantation mask or as a part of an implantation mask.
The process may be completed, after stage d) by deploying an isolator on the substrate, followed by the formation of contact points on the source, drain and gate areas of the transistors.
Furthermore, the process may comprise, additionally, connecting the gate of the first transistor to a doped zone separate from the first doped zone and forming one of the source and drain of the second transistor, and connecting the gate of the second transistor to the first doped zone.
In the example considered in the present description, where the source of the second transistor is constituted by the second doped zone, the gate of the first MOS transistor is connected to the drain of the second transistor, in other words to the third doped zone.
Where the limiter means comprises a diode, the process for manufacturing the device comprises the following successive stages:
a) preparation in a substrate of a so-called active zone having a first conductivity type, intended to receive the first transistor and the diode,
b) formation of a first and a second gate above the active zone corresponding to the first transistor and the diode respectively, the gates being separated from the substrate by a gate insulator,
c) formation of source and drain areas of the first transistor and of said second doped zone, formation of the first doped zone placed between a channel of the first transistor and the second doped zone, and formation of the third doped zone separated from the first doped zone by the second doped zone, the source and drain areas and the first doped zone being formed by self-aligned implantations on the first gate,
d) formation of a conductive layer in contact with the first doped zone and the second doped zone so as to connect them electrically.
The different doped areas or zones formed during stage c) may be so formed in any order.
The process may be completed, after stage d), by deploying an isolator on the substrate followed by the formation of contact points on the source and drain areas and on the third doped zone.
It may additionally comprise the interconnection of the third doped zone and of the gate of the first transistor.
The device is preferably made on an SOI type substrate, in other words a substrate having a thin silicon surface layer, insulated by a layer of oxide buried in a silicon block acting as a support.
The components are in this case formed in the thin surface layer. His layer is not generally doped initially. However, the preparation stage a) may comprise a slight doping of the first conductivity type, of all or part of the thin surface layer.
Additionally, the active area may be delimited by local oxidation of the thin surface layer to form field oxide blocks. This surface insulation technique is usually known as xe2x80x9cLOCOSxe2x80x9d (Localised Oxidation of Silicon). The active area may also be delimited by Shallow Trench Isolation.
The active zone is thus completely insulated by the field oxide blocks and by the buried oxide layer.
Other characteristics and advantages of the present invention will emerge more clearly from the following description, with reference to the appended drawings. This description is given purely by way of illustration and non-restrictively.